Semiconductor integrated circuit device

ABSTRACT

An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Application No. 2011-185608 filed onAug. 29, 2011 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to semiconductor integrated circuitdevices, and more particularly relates to techniques effective in theinterface circuit for coupling other semiconductor integrated circuitdevice.

When a semiconductor integrated circuit device, such as an SDRAM(Synchronous Dynamic Random Access Memory), is coupled to asemiconductor integrated circuit device, such as a microcomputer, aninterface circuit is required inside the respective devices. Thisinterface circuit is designed based on a specification complying withthe international standard defined for each type of SDRAM.

In the SDRAM, the DDR (Double Data Rate) standard, the DDR2 standard,the DDR3 standard, the LPDDR (Low Power Double Data Rate) standard, theLPDDR2 standard, and the like have been established.

The DDR standard includes a DDR function to read and write data at bothrising and falling of the clock signal, so that data is transferred at aspeed of twice the internal clock frequency of an SDRAM.

In the DDR2 standard, because the clock frequency in outputting data tothe outside is twice the internal clock frequency of an SDRAM, the datacan be transferred four times the internal clock frequency. In the DDR3standard, because the clock frequency in outputting data to the outsideis four times the internal clock frequency of an SDRAM, the data can betransferred eight times the internal clock frequency.

Recently, while the data transfer rate of the SDRAM has been increased,reliable data transfer is also required. In an SRAM having the DDRfunction, because data is taken in at both the rising edge (the risingof a waveform) and the falling edge (the falling of a waveform) of aclock signal, not only timing margins between the rising edge of a clocksignal and the rising edge and falling edge of data but timing marginsbetween the falling edge of the clock signal and the rising edge andfalling edge of the data need to be considered.

Furthermore, in the case of the LPDDR2 standard, the frequency of anexternal clock signal is up to 533 MHz (data transfer rate is 1066Mbps), while in the case of the DDR3 SDRAM standard, the frequency of anexternal clock signal is specified up to 800 MHz (data transfer rate is1600 Mbps). As the data transfer rate increases, the data transferperiod decreases and therefore it is increasingly difficult to securethe timing margins.

SUMMARY

In the interface circuit with respect to the SDRAM having the DDRfunction, as described in Japanese Patent Laid-Open No. 2000-156082(Patent Document 1), used is an input buffer circuit which includes adifferential amplifier circuit receiving a single-ended input signal atone input terminal and receiving a reference voltage at other inputterminal.

In this differential amplifier circuit, the characteristic of an outputsignal of the differential amplifier differs between when the voltage ofan input signal is larger than a reference voltage (the input signal isat a ‘High’ level) and when it is smaller (the input signal at a ‘Low’level). Specifically, in the differential amplifier circuit, there is adifference between a response time from the rising of an input signalwaveform until an output signal waveform varies in response thereto, anda response time from the falling of the input signal waveform until theoutput signal waveform varies in response thereto.

A semiconductor integrated circuit device is coupled to an SDRAM bymeans of a plurality of signal lines for transferring data. Accordingly,in an interface circuit of the semiconductor integrated circuit device,an input buffer circuit is provided for each bus. In order to take inmulti-bit data into the semiconductor integrated circuit device, aplurality of input buffer circuits preferably outputs output signals atsubstantially the same timing, respectively.

However, as stated above, if there is a difference in the response timebetween the rising and the falling of the input signal waveform in thedifferential amplifier circuit, the timing of the output signal willshift from each other among a plurality of input buffer circuits,resulting in a pin-to-pin skew. This causes a decrease in the timingmargin.

The present invention has been made in view of the above circumstancesand improves the characteristic of the output signal of a differentialamplifier circuit.

The other purposes and the new features of the present invention willbecome clear from the description of this specification and theaccompanying drawings.

The following explains briefly the outline of a typical invention amongthe inventions disclosed in the present application. A differentialamplifier circuit including a first differential input section thatreceives an input signal from an external connection terminal and asecond differential input section that receives a reference voltagedetects a current generated in the first differential input section, andfeeds this back to a tail current source to control a tail current.

The following explains briefly the effect acquired by the typicalinvention among the inventions disclosed in the present application. Thecharacteristic of the output signal of a differential amplifier circuitcan be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of the configuration of asemiconductor integrated circuit device 1 and a semiconductor integratedcircuit device 2 according to the First Embodiment of the presentinvention;

FIG. 2 is an explanatory view of a connection portion between thesemiconductor integrated circuit device 1 and the semiconductorintegrated circuit device 2 in FIG. 1;

FIGS. 3A and 3B are explanatory views showing an example of theconfiguration in an I/O cell of FIG. 2;

FIG. 4 is an explanatory view showing an example of an input buffer usedin an I/O cell which the present inventor studied;

FIGS. 5A to 5C are explanatory views showing an example of a DCcharacteristic in a differential amplifier circuit of FIG. 4;

FIG. 6 is an explanatory view showing an example of an input waveformand an output waveform in the differential amplifier circuit of FIG. 4;

FIG. 7 is a conventional circuit diagram showing an example of theconfiguration in the input buffer of FIG. 3;

FIGS. 8A to 8C are explanatory views showing an example of a DCcharacteristic in a differential amplifier circuit of FIG. 7;

FIG. 9 is an explanatory view showing an example of the timings of aninput waveform and an output waveform in the differential amplifiercircuit of FIG. 7;

FIG. 10 is an explanatory view showing an example of an input bufferaccording to the Second Embodiment of the present invention;

FIG. 11 is an explanatory view showing an example of the configurationof an I/O cell to which a clock signal is input, according to the ThirdEmbodiment of the present invention;

FIG. 12 is an explanatory view showing an example of the configurationof an I/O cell to which a clock signal is input, according to the FourthEmbodiment of the present invention;

FIG. 13 is an explanatory view showing an operation example of a delayadjustment circuit provided in the I/O cell of FIG. 12; and

FIG. 14 is an explanatory view showing a basic configuration of adifferential amplifier circuit according to the First Embodiment of thepresent invention.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. In all the drawingsfor explaining the embodiments, the same symbol is attached to the samemember, as a principle, and the repeated explanation thereof is omitted.

First Embodiment

FIG. 1 is a block diagram showing an example of the configuration inwhich a semiconductor integrated circuit device 1 and a semiconductorintegrated circuit device 2 according to the First Embodiment of thepresent invention are coupled to each other, FIG. 2 is an explanatoryview of a connection portion between the semiconductor integratedcircuit device 1 and the semiconductor integrated circuit device 2 inFIG. 1. FIGS. 3A and 3B are explanatory views showing an example of theconfiguration in an I/O cell of FIG. 2. FIG. 4 is an explanatory viewshowing an example of an input buffer used in an I/O cell which thepresent inventor studied. FIGS. 5A to 5C are explanatory views showingan example of a DC characteristic in a differential amplifier circuit ofFIG. 4. FIG. 6 is an explanatory view showing an example of an inputwaveform and an output waveform in the differential amplifier circuit ofFIG. 4. FIG. 7 is a circuit diagram showing an example of theconfiguration in the input buffer of FIG. 3A. FIGS. 8A to 8C areexplanatory views showing an example of a DC characteristic in thedifferential amplifier circuit of FIG. 7. FIG. 9 is an explanatory viewshowing an example of the timings of an input waveform and an outputwaveform in the differential amplifier circuit of FIG. 7.

Hereinafter, the embodiments will be described in detail.

In the First Embodiment, to the semiconductor integrated circuit device1 including a microcomputer and the like, as shown in FIG. 1, thesemiconductor integrated circuit device 2 is coupled. The semiconductorintegrated circuit device 2 is, for example, an SDRAM having the DDRfunction, such as DDR, DDR2, DDR3, or LPDDR2, or a nonvolatile memory,such as a flash memory, an MRAM (Magnetic Random Access Memory), and anFeRAM (Ferroelectric Random Access Memory) having the DDR function.Usually, the semiconductor integrated circuit device 1 and thesemiconductor integrated circuit device 2 are mounted on a printedcircuit board or the like in a separate package, respectively, and arecoupled to each other, but it is also possible to couple these devicesto each other in one package as a multi-chip module, for example.

An I/O area 1 a is provided in four side sections of the semiconductorintegrated circuit device 1, respectively. A core area 3 is formed inthe semiconductor integrated circuit device 1 so as to be surrounded bythe I/O area 1 a. Note that FIG. 1 also shows a layout (arrangement)other than the configuration.

The core area 3 is constituted by including a plurality of internalcircuits, such as a CPU4, a RAM5, a memory interface controller 6, and areference voltage generation circuit 7 (FIG. 2).

The CPU4 manages the main control in the semiconductor integratedcircuit device 1. The RAM5 is a volatile semiconductor memory and isused for temporary storage of data.

Moreover, in the I/O area 1 a, a plurality of I/O cells performinginputting/outputting of a signal with respect to the outside isprovided, respectively. The I/O cells are each formed in a rectangularshape, for example, and are linearly arranged so that one short sidethereof is parallel to one arbitrary side of a semiconductor chip.

The semiconductor integrated circuit device 1 includes an I/O cellportion 8 including a plurality of I/O cells to which the semiconductorintegrated circuit device 2 is coupled. The I/O cell portion 8 is aninterface circuit with respect to the semiconductor integrated circuitdevice 2, and is coupled to an I/O cell portion 2 a including aplurality of I/O cells, the I/O cell portion 2 a serving as an interfacecircuit provided in the semiconductor integrated circuit device 2,respectively. The memory interface controller 6 carries out an operationcontrol of the I/O cell portion 8 under the control of the CPU4 and thelike to be described later. The reference voltage generation circuit 7is a circuit generating a reference voltage VREF supplied to the I/Ocell portion 8.

FIG. 2 is an explanatory view in the connection portion between thesemiconductor integrated circuit device 1 and the semiconductorintegrated circuit device 2 in FIG. 1 when data read from thesemiconductor integrated circuit device 2 is input to the semiconductorintegrated circuit device 1. Although not shown here, when data outputfrom the semiconductor integrated circuit device 1 is written to thesemiconductor integrated circuit device 2, the relationship betweentransmission and reception is reversed.

In the semiconductor integrated circuit device 1, I/O cells 81-88, towhich data signals DQ0-DQ7 are input and output, and an I/O cell 89, towhich data strobe signals DQS and DQSB serving as clock signals used fordata transfer are input and output, are provided. Similarly, in thesemiconductor integrated circuit device 2, I/O cells 2 a 1-2 a 8, towhich the data signals DQ0-DQ7 are input and output, and an I/O cell 2 a9, to which the clock signals DQS and DQSB are input and output, areprovided. A memory internal circuit 2 b is coupled to the I/O cells 2 a1-2 a 9.

An input enable signal IE output from the memory interface controller 6is input to the I/O cells 81-89, respectively. The input enable signalIE is a control signal for causing an input buffer constituting the I/Ocell to operate. Moreover, the reference voltage VREF which thereference voltage generation circuit 7 generates is supplied to the I/Ocells 81-89.

Flip-flop portions 61-69 are provided in the memory interface controller6. Note that, in the memory interface controller 6 of FIG. 2, while onlya configuration example in which the memory interface controller 6 iscoupled to the input buffer side of the I/O cells 81-89 is shown, aconfiguration in which the memory interface controller 6 is coupled tothe output buffer side of the I/O cells 81-89 is omitted.

The flip-flop portions 61-69 are each constituted by two flip-flops FF1and FF2. For example, in the case of the flip-flop portion 61 coupled tothe I/O cell 81, an internal data signal DQI0 output from the I/O cell81 is input to data terminals of the flip-flops FF1 and FF2,respectively.

Moreover, an internal clock signal DQSIB output from the I/O cell 89 isinput to a clock input terminal of the flip-flop FF1, and an internalclock signal DQSI output from the I/O cell 89 is input to a clock inputterminal of the flip-flop FF2. The internal clock signal DQSIB is aninverted signal of the internal clock signal DQSI. The output terminalsof the flip-flops FF1 and FF2 are coupled in common to an outputterminal DQL0 of the flip-flop portion, and data is output to the RAM5or the like.

Hereinafter, the connection configuration between the flip-flop portions62-69 and the I/O cells 82-89 is also the same as that in the case ofthe flip-flop portion 61 and the I/O cell 81 and therefore thedescription thereof is omitted.

Here, the operation during data read in FIG. 2 (data transfer from thesemiconductor integrated circuit device 2 to the semiconductorintegrated circuit device 1) is described.

During data read, data is output from the memory internal circuit 2 b insynchronization with a memory internal clock. Here, the output data istransferred to the semiconductor integrated circuit device 1 using a DDRdata transfer system, for example.

In this case, assume that a plurality of buses is provided in parallelfrom the memory internal circuit 2 b to the I/O cells 2 a 1-2 a 8, andthat one bus has one-bit data.

Two buses (corresponding to two bits) are combined into one, and data istransferred at a double frequency. The clock signal is also outputtogether with data, but in the case of the DDR data transfer system,differential clock signals are transmitted from the I/O cell 2 a 8 tothe semiconductor integrated circuit device 1 side.

Here, the differential clock signals are the clock signals DQS and DQSB.In the case of DDR, the frequency of the clock signals DQS and DQSB isthe same as that of the memory internal clock (in the case of DDR2 it isthe double frequency, and in the case of DDR3 it is the quadruplefrequency).

The differential clock signals DQS and DQSB and the data signals DQ0-DQ7are taken into the semiconductor integrated circuit device 1 via the I/Ocells 81-89 of the semiconductor integrated circuit device 1.

As described above, the reference voltage VREF which the referencevoltage generation circuit 7 generates is supplied to the respective I/Ocells 81-89, and an input signal is taken into the respective I/O cells81-89 with reference to the reference voltage VREF.

The internal clock signals DQSI and DQSIB of the semiconductorintegrated circuit device 1 output from the I/O cell 89 are input to therespective flip-flops FF1 and FF2 in the flip-flop portions 61-69 of thememory interface controller 6.

In the internal input data signals DQI0-DQI7 of the semiconductorintegrated circuit device 1, data is taken in in synchronization withthe rising timing of the internal clock signals DQSI and DQSIB by theflip-flops FF1 and FF2 of the flip-flop portions 61-69. With thisoperation, data can be read for every half period of the clock signalsDQS and DQSB.

FIGS. 3A and 3B are explanatory views showing an example of theconfiguration in the I/O cell 81(-89) of FIG. 2.

The I/O cell 81(-89) is constituted by an input buffer 9 and an outputbuffer 10 as shown in the view. An input section of the input buffer 9and an output section of the output buffer 10 are coupled in common to apad PAD coupled to an I/O terminal that is an external connectionterminal of the semiconductor integrated circuit device 1.

As shown in FIG. 3A, in the I/O cell 81(-88) for a data signal, thereference voltage VREF, which the reference voltage generation circuit 7generates, and the input enable signal IE are input to the input buffer9. Then, the memory interface controller 6 is coupled to the outputsection of the input buffer 9 and the input section of the output buffer10, respectively.

Moreover, as shown in FIG. 3B, the I/O cell 89 for the clock signal isconstituted by the input buffer 9 and output buffers 10 and 10 a, anddifferential clock signals are input to the input buffer 9. Theconfiguration differs between the I/O cell for a data signal and the I/Ocell for the clock signal, in that the input buffer of the I/O cell fora data signal amplifies a difference between the reference voltage VREFand an input signal while the input buffer of the I/O cell for the clocksignal amplifies a difference between the differential signals.

FIG. 14 is a circuit configuration diagram showing an example of adifferential amplifier circuit according to the embodiment. Adifferential signal input section is configured such that an inputsignal is input to the gate of a transistor 16 which is a firstdifferential input section and the reference voltage is input to thegate of a transistor 17 which is a second differential amplifiersection. The source terminal of the transistor 16 and the sourceterminal of the transistor 17 are coupled to the drain terminal of atransistor 18 serving as a tail current source, and a current from thetransistor 16 and a current from the transistor 17 flow to a powersupply voltage VSSQ via the transistor 18. When an input signal having avoltage amplitude between a power supply voltage VDDQ and the powersupply voltage VSSQ is input, the operation point voltage of thedifferential amplifier circuit will vary in response to the voltage ofthe input signal and the characteristic will vary. In order to moderatea change in the characteristic, the gate voltage of the transistor 18 iscontrolled in response to the input signal, thereby controlling the tailcurrent.

FIG. 4 is an explanatory view showing an example of the input buffer 9used in an I/O cell which the present inventor studied.

The input buffer 9 includes two differential amplifier circuits 11 and12 and an inverter 13. Although two differential amplifier circuits areused in this example, the input buffer 9 may be constituted by one, orthree or more differential amplifier circuits in accordance with arequired gain.

The differential amplifier circuit 11 is a circuit, to which a functionto use the differential amplifier circuit shown in FIG. 14 in the inputbuffer is added. The differential amplifier circuit 11 is constituted byresistors 14, 14 a and 15 used as a load element, transistors 16 and 17used as an input transistor, a transistor 18 used as the tail transistorserving as a tail current source, and in addition a transistor 19 forcarrying out an input operation control. The differential amplifiercircuit 12 is constituted by transistors 20-24. Moreover, the inverter13 is constituted by transistors 25 and 26.

The transistors 20, 21 and 25 are each constituted by a P-channel MOS(Metal Oxide Semiconductor) transistor, and the transistors 16-19, 22-24and 26 are each constituted by an N-channel MOS transistor.

The power supply voltage VDDQ is coupled to one connection of therespective resistors 14 and 15, one connection of the transistor 20, oneconnection of the transistor 21, one connection of the transistor 25,and a backgate of the respective transistors 20, 21 and 25,respectively.

One connection of the resistor 14 a is coupled to the other connectionof the resistor 14. One connection of the transistor 16 and the gate ofthe transistor 23 are coupled to the other connection of the resistor 14a, respectively. One connection of the transistor 17 and the gate of thetransistor 22 are coupled to the other connection of the resistor 15,respectively.

The gate of the transistor 16 is one input terminal of the differentialamplifier circuit 11, and a signal output from the semiconductorintegrated circuit device 2 is input to this gate, and the gate of thetransistor 17 is other input terminal of the differential amplifiercircuit 11, and the reference voltage VREF which the reference voltagegeneration circuit 7 generates is input to this gate.

One connection of the transistor 18 is coupled to the other connectionof the transistor 16 and the other connection of the transistor 17, andthe other connection of the transistor 19 is coupled to the otherconnection of the transistor 18.

A connection (node D) between the resistor 14 and the resistor 14 a iscoupled to the gate of the transistor 18, and one connection of thetransistor 19 is coupled to the other connection of the transistor 18.

Moreover, the input enable signal IE output from the memory interfacecontroller 6 is input to the gate of the transistor 19. The referencepotential VSSQ is coupled to the other connection of the transistor 19and the backgate of the respective transistors 16, 17, 18 and 19,respectively.

One connection of the transistor 22, the gate of the transistor 25, andthe gate of the transistor 26 are coupled to the other connection of thetransistor 20, respectively. The gate of the transistor 21, the otherconnection of the transistor 21, and one connection of the transistor 23are coupled to the gate of the transistor 20, respectively.

The other connection of the transistor 23 and one connection of thetransistor 24 are coupled to the other connection of the transistor 22,respectively.

The input enable signal IE is coupled to the gate of the transistor 24.Moreover, the reference potential VSSQ is coupled to the otherconnection of the transistor 24, the backgate of the transistor 24, andthe backgate of the respective transistors 22 and 23, respectively.

Furthermore, one connection of the transistor 26 is coupled to the otherconnection of the transistor 25, and this connection serves as theoutput section of the input buffer 9. The reference potential VSSQ iscoupled to the other connection and the backgate of the transistor 26,respectively.

As shown in FIG. 4, the input buffer 9 is specified to receive a signalby means of the differential amplifier circuit using the reference powersupply VREF. In the first stage differential amplifier circuit 11, thereference voltage VREF is coupled to the gate of the transistor 17, anda signal is input to the gate of the other transistor 16.

In the case of this example, because a gain cannot be secured in thefirst stage differential amplifier circuit 11, the second stagedifferential amplifier circuit 12 is provided for securing a necessarygain. The differential amplifier circuit 12 is of a current mirror type,and amplifies so that the amplitude of a signal sent to the inverter 13in the subsequent stage can be obtained sufficiently.

The signal amplified by the differential amplifier circuit 12 isinverted by the inverter 13, and output as an output signal having avoltage amplitude of the power supply voltage VDDQ minus the referencepotential VSSQ of the input buffer 9.

Next, the operation of the differential amplifier circuit 11 provided inthe input buffer 9 according to the embodiment is described.

In the differential amplifier circuit 11 of the input buffer 9, as shownin the view, a signal is negatively fed back to the gate of thetransistor 18 used as the tail transistor serving as the tail currentsource.

First, the input enable signal IE is input to the gate of the transistor19, so that the input buffer 9 becomes in an operable state. Then, whenthe input data signal becomes ‘Low’, a current I1 (a source-draincurrent IDS) flowing through the transistor 16 will decrease and thepotential at the connection (node D) between the resistor 14 and theresistor 14 a will increase. Because this potential is input (negativelyfed back) to the gate of the transistor 18, the gate potential of thetransistor 18 increases and thereby a tail current amount I_TAIL isadjusted in an increasing direction.

Next, when the input data signal becomes ‘High’, the current I1 willflow more and therefore the potential at the node D will decrease. Thus,the gate potential (negative feedback) of the transistor 18 decreases,so that the tail current amount I_TAIL is adjusted in a decreasingdirection.

FIGS. 5A to 5C are explanatory views showing an example of the DCcharacteristic when the input voltage is varied in the differentialamplifier circuit 11.

FIG. 5A shows the characteristic of the input data signal (indicated bya solid line) and the reference voltage VREF (indicated by a dottedline) input to the differential amplifier circuit 11. FIG. 5B shows thecharacteristics of the potential (indicated by a solid line) at aconnection (a node A in FIG. 4) between the resistor 14 a and thetransistor 16, the potential (indicated by a dotted line) at aconnection (a node B of FIG. 4) between the resistor 15 and thetransistor 17, and the potential (indicated by a dashed-dotted line) ata connection (a node C) between the transistors 16, 17 and 18. FIG. 5Cshows the characteristics of the tail current I_TAIL (indicated by asolid line) flowing through the transistor 18, the current I1 (indicatedby a dotted line) flowing through the transistor 16, and a current I2(indicated by a dashed-dotted line) flowing through the transistor 17.

In FIG. 5A, the input data signal (solid line) input to the differentialamplifier circuit 11 transitions in terms of DC voltage from 0 V (thereference potential VSSQ) to the power supply voltage VDDQ. In contrast,the power supply voltage VREF (dotted line) is maintained always at asubstantially constant voltage value.

Each voltage at the nodes A to C at this time has a waveform shown inFIG. 5B, and each current of the currents I1, I2, and I_TAIL has awaveform shown in FIG. 5C.

As described above, in the differential amplifier circuit 11, when theinput data signal is ‘Low’, the current amount of the current I1decreases and the potential at the node D (FIG. 4) increases, and as aresult the gate potential of the transistor 18 increases and the currentamount of I_TAIL increases.

Moreover, when the input data signal becomes ‘High’, the current I1flows more and therefore the potential at the node D decreases and as aresult the gate potential of the transistor 18 decreases and accordinglythe tail current amount I_TAIL decreases.

Thus, as shown in FIGS. 5A to 5C, in the differential amplifier circuit11, either when the input data signal is ‘Low’ (when the input datasignal has a voltage lower than the reference voltage VREF) or when theinput data signal is ‘High’ (when the input data signal has a voltagehigher than the reference voltage VREF), a variation in the voltage atthe node C shown in FIG. 5B and a variation in the tail current I_TAILshown in FIG. 5C can be reduced.

In this manner, if a variation in the voltage at the node C and avariation in the tail current I_TAIL decrease by causing the transistor18 to operate in a negative feedback mode, then as shown in FIG. 6, adelay difference between a delay T1 from the rising of the waveform ofthe input data signal input to the differential amplifier circuit 11 tothe rising of the output signal waveform and a delay T2 from the fallingof the input data signal waveform to the falling of the output signalwaveform decreases, and an effect of reducing the skew of the signalinput to the flip-flop can be obtained.

As a comparative example, FIG. 7 shows an example of the configurationaccording to a conventional circuit in the input buffer 9 of FIGS. 3Aand 3B.

An input buffer 100 includes differential amplifier circuits 101 and 102and an inverter 103, as shown in the view. The differential amplifiercircuit 101 is constituted by resistors 104 and 105 and transistors106-108, and the differential amplifier circuit 102 is constituted bytransistors 109-113.

Moreover, the inverter 103 includes transistors 114 and 115. Thetransistors 106-108, 111-113 and 115 are each constituted by anN-channel MOS transistor, and the transistors 109, 110 and 114 are eachconstituted by a P-channel MOS transistor.

The power supply voltage VDDQ is coupled to one connection of therespective resistors 104 and 105, one connection of the respectivetransistors 109 and 110, one connection of the transistor 114, and thebackgate of the respective transistors 109, 110 and 114, respectively.

One connection of the transistor 106 and the gate of the transistor 112are coupled to the other connection of the resistor 104, respectively.One connection of the transistor 107 and the gate of the transistor 111are coupled to the other connection of the resistor 105, respectively.

A signal output from the semiconductor integrated circuit device 2 isinput to the gate of the transistor 106, and the reference voltage VREFis input to the gate of the transistor 107.

One connection of the transistor 108 is coupled to the other connectionof the transistor 106 and the other connection of the transistor 107,and a constant voltage is input to the gate of the transistor 108.Moreover, the reference potential VSSQ is coupled to the otherconnection of the transistor 108 and the backgate of the respectivetransistors 106-108, respectively.

One connection of the transistor 111 and the gates of the transistors114 and 115 are coupled to the other connection of the transistor 109,respectively. The gate of the transistor 110, the other connection ofthe transistor 110, and one connection of the transistor 112 are coupledto the gate of the transistor 109, respectively.

One connection of the transistor 113 is coupled to the other connectionof the respective transistors 111 and 112, and a constant voltage isinput to the gate of the transistor 113. Moreover, the referencepotential VSSQ is coupled to the other connection and the backgate ofthe transistor 113 and the backgate of the respective transistors 111and 112, respectively.

One connection of the transistor 115 is coupled to the other connectionof the transistor 114, and this connection serves as the output sectionof the input buffer 100. Moreover, the reference potential VSSQ iscoupled to the other connection and the backgate of the transistor 115,respectively.

In the case of the configuration of the input buffer 100 of FIG. 7, thefirst-stage differential amplifier circuit 101 has a problem that theoperation becomes unbalanced between during the rising of the input datasignal waveform and during the falling of the input data signalwaveform.

FIGS. 8A to 8C are explanatory views showing an example of DCcharacteristic in the differential amplifier circuit of FIG. 7,respectively. FIG. 9 is an explanatory view showing an example of thetimings of the input data signal waveform and the output signal waveformin the differential amplifier circuit 101.

A solid line in FIG. 8A shows the input data signal, and transitionsfrom the reference potential VSSQ to the power supply voltage VDDQ interms of DC voltage. In contrast, the reference voltage VREF indicatedby a dotted line is always maintained at a substantially constantvoltage value.

The voltages at the nodes A1-C1 at this time correspond to the voltagewaveforms shown in FIG. 8B, and the currents I11, I21, and I_TAIL1correspond to the current waveforms shown in FIG. 8C. Here, the node A1is the connection between the resistor 104 and the transistor 106, thenode B1 is the connection between the resistor 105 and the transistor107, and the node C1 is the connection between the transistors 106-108.

Moreover, the current I11 is a current flowing through the transistor106, the current I21 is a current flowing through the transistor 107,and the current I_TAIL1 is a tail current flowing through the transistor108.

When the input data signal is a “Low” signal, because the transistor 106is turned off, the potential at the node A rises to the power supplyvoltage VDDQ and the potential at the node B on the opposite side ispulled to the reference potential VSSQ side.

Moreover, when the input data signal becomes a “High” signal, thetransistor 116 on the input side comes into an ON state, and forexample, when the potential of the input data signal becomes equal to orgreater than 0.6 V, the current flowing through the transistor 106 onthe input side becomes larger and thus the potential at the node A1 ispulled to the reference potential VSSQ side and the potential at thenode B1 is pulled to the power supply voltage VDDQ side.

However, as shown in FIG. 8C, the reference voltage VREF issubstantially constant, and therefore when the potential of the inputdata signal becomes a “High” signal, the current amount as a wholeincreases, while when the input data signal is a “Low” signal, thecurrent amount decreases.

Therefore, the voltage at the node C (the node C is the drain of thetransistor 108 that is the tail transistor) and the tail current willdramatically vary between ‘High’ and ‘Low’ of the input data signal.Thus, as shown in FIG. 9 the difference between a delay T3 from therising of the input data signal waveform to the rising of the outputsignal waveform and a delay T4 from the falling of the input data signalwaveform to the falling of the output signal waveform will increase.Because whether the input data signal is ‘High’ or ‘Low’ differs forevery pin, this causes an increase in the pin-to-pin skew of the signalinput to the flip-flop.

On the other hand, in the differential amplifier circuit 11 shown inFIG. 4, by introducing the negative feedback operation into thetransistor 18 serving as the tail transistor, the voltage variation atthe node C decreases and the difference between the delay T1 (FIG. 6)and the delay T2 (FIG. 6) can be reduced, and therefore the skew isreduced and the timing margin between the clock signal and the datasignal input to the flip-flop will be improved.

Thus, according to the First Embodiment, the signal skew due to theinput buffer can be significantly reduced and the failure and the likein reading data can be reduced.

Moreover, because a failure of the semiconductor integrated circuitdevice 1 associated with a reduction in the timing margin due to theskew can be reduced, the reliability of the semiconductor integratedcircuit device 1 can be improved while increasing the yield.

Furthermore, in the First Embodiment, the input buffer provided in theI/O cells 81-88 provided in the semiconductor integrated circuit device1 has been described, but the input buffer provided in the I/O cells 2 a1-2 a 8 of the semiconductor integrated circuit device 2 may also havethe same configurations as those of FIGS. 3A and 3B and FIG. 4.

Variation of the First Embodiment

In the First Embodiment described above, in the differential amplifiercircuit 11 of the input buffer 9 (FIG. 4), the current on the input sideis detected using the resistors 14 and 14 a, but a technique is nowdescribed, in which the detection of the current on the input side ismade by means other than the resistors.

FIG. 10 is an explanatory view showing an example of an input bufferaccording to variation of the First Embodiment of the present invention.

The input buffer 9 includes differential amplifier circuits 11 a and 12and the inverter 13.

The differential amplifier circuit 11 a is constituted by the resistor14 a and the transistors 16-19, 28 and 29. The transistors 28 and 29 areeach constituted by a P-channel MOS transistor.

The power supply voltage VDDQ is coupled to one connection of thetransistor 28, one connection of the transistor 29, and the backgate ofthe respective transistors 28 and 29, respectively. Moreover, a biasvoltage is supplied to the gates of transistors 28 and 29, respectively.Then, the values of currents flowing through the transistors 28 and 29are adjusted with the bias voltage supplied to the transistors 28 and29.

One connection of the resistor 14 a and the gate of the transistor 18are coupled to the other connection of the transistor 28, respectively,and one connection of the transistor 17 is coupled to the otherconnection of the transistor 29.

Other than this, the connection configurations of the transistors 16-19in the differential amplifier circuit 11 a, the differential amplifiercircuit 12, and the inverter 13 are the same as those of FIG. 4 of theFirst Embodiment described above, and therefore the description thereofis omitted.

In this manner, in the differential amplifier circuit 11 a of FIG. 10,the resistor 14 is replaced with the P-channel MOS transistor 28 and theresistor 15 is replaced with the P-channel MOS transistor 29. Note thatthe operation is the same as that of FIG. 4 of the First Embodimentdescribed above, and therefore the description thereof is omitted.

Thus, also in the variation of the First Embodiment, the signal skew dueto the input buffer can be significantly reduced and the failure and thelike in reading data can be reduced. Moreover, because the failure ofthe semiconductor integrated circuit device 1 can be reduced, anincrease in the yield and an improvement in the reliability can berealized.

Furthermore, also in the variation of the First Embodiment, the inputbuffer provided in the I/O cells 2 a 1-2 a 8 of the semiconductorintegrated circuit device 2 may also have the same configurations asthose of FIG. 10.

Second Embodiment

FIG. 11 is an explanatory view showing an example of the configurationof an I/O cell, to which differential signals are input, according tothe Second Embodiment of the present invention.

Outline of the Second Embodiment

According to the outline of the Second Embodiment of the presentinvention, a semiconductor integrated circuit device includes an I/Ocircuit (I/O cell 89) constituted by: a first input buffer (input buffer30) to which one of differential signals is input and a second inputbuffer (input buffer 31) to which the other one of the differentialsignals is input;

and a first output buffer (output buffer 32) to which one of thedifferential signals is input and a second output buffer (output buffer33) to which the other one of the differential signals is input. Thefirst input buffer includes a first differential amplifier circuitamplifying and outputting a first signal (clock signal DQS) of thedifferential signals. The second input buffer includes a seconddifferential amplifier circuit amplifying and outputting a second signal(clock signal DQSB) that is an inverted signal of the first signal ofthe differential signals.

Hereinafter, based on the above-described outline, the embodiment isdescribed in detail.

In the Second Embodiment, an I/O cell whose input and output signals aredifferential is described. The examples of the I/O cell whose input andoutput signals are differential include the I/O cell 89 (FIG. 2) towhich the clock signals DQS and DQSB output from the semiconductorintegrated circuit device 2 (FIG. 2) are input.

FIG. 11 is a block diagram showing an example of the configuration ofthe I/O cell 89.

Differential input signals are input to the I/O cell 89 as the inputsignals, and the I/O cell 89 includes the input buffers 30 and 31 andthe output buffers 32 and 33 as shown in the view.

The input section of the input buffer 30 and the output section of theoutput buffer 32 are coupled in common to a pad P1 coupled to the I/Oterminal that is an external connection terminal of the semiconductorintegrated circuit device 1. Moreover, the input section of the inputbuffer 31 and the output section of the output buffer 33 are coupled incommon to a pad P2 coupled to an I/O terminal that is an externalconnection terminal of the semiconductor integrated circuit device 1.

The clock signal DQS is input to the input buffer 30 via the pad P1, andthe clock signal DQSB that is an inverted signal of the clock signal DQSis input to the input buffer 31 via the pad P2.

Moreover, the input buffers 30 and 31 have a connection configurationsimilar to that of the input buffer used in the I/O cells 81-88. Here,because the connection configuration is the same as that of the inputbuffer 9 in FIG. 4 of the First Embodiment described above or the inputbuffer 9 in FIG. 10, the description thereof is omitted. The connectionconfiguration differs from that of the input buffer 9 of FIG. 4 only inthat in the input buffer 30 the clock signal DQS is input to the gate ofthe transistor 16 and that in the input buffer 31 the clock signal DQSBis input to the gate of the transistor 16.

In the case of a typical input buffer to which differential signals areinput, for example, in FIG. 7, the clock signal DQS is input to the gateof the transistor 106, and the clock signal DQSB is input to the gate ofthe transistor 107.

On the other hand, in the I/O cell 89, as with the input buffer 9 of theI/O cells 81-88, in the differential amplifier circuit 11 that isprovided in two input buffers 30 and 31, respectively, the clock signalsDQS and DQSB are sensed with reference to the reference voltage VREF.Thereby, a delay between the data signal-output from the input buffer 9and the clock signals DQS and DQSB output from the input buffers 30 and31 of the I/O cell 89 can be minimized.

Thus, in the Third Embodiment, a skew between the clock signals DQS andDQSB that are differential signals and the input data signal that is asingle-ended signal can be reduced. Note that, in the case of a typicalinput buffer (differential amplifier circuit) to which differentialsignals are input, for example, in FIG. 7, the clock signal DQS is inputto the gate of the transistor 106, and the clock signal DQSB is input tothe gate of the transistor 107. Even if this typical input buffer isused for differential signals and the input buffer of the FirstEmbodiment is used for a single-ended signal, the skew can be reducedalthough not as good as in the Second Embodiment.

Moreover, in the Second Embodiment, while the input buffer provided inthe I/O cell 89 provided in the semiconductor integrated circuit device1 has been described, the input buffer provided in the I/O cell 2 a 9 ofthe semiconductor integrated circuit device 2 may also have the sameconfiguration as that of FIG. 4.

Third Embodiment

FIG. 12 is an explanatory view showing an example of the configurationof an I/O cell, to which a clock signal is input, according to the ThirdEmbodiment of the present invention. FIG. 13 is an explanatory viewshowing an operation example of a delay adjustment circuit provided inthe I/O cell of FIG. 12.

In the Third Embodiment, the I/O cell 89 has a configuration, in which adelay adjustment circuit 34 is added to the same configuration as thatof FIG. 11 of the Second Embodiment described above. The delayadjustment circuit 34 is constituted by inverters 35-40.

The inverters 35-37 and the inverters 38-40 are coupled in series,respectively. The output section of the input buffer 30 is coupled tothe input section of the inverter 35, and the output section of theinput buffer 31 is coupled to the input section of the inverter 38. Asignal ZB is output from the output section of the inverter 37, while asignal Z is output from the output section of the inverter 40. The delayadjustment circuit 34 is a circuit that adjusts a delay time (eliminatesa delay time difference) between a signal IN output from the inputbuffer 30 and a signal INB output from the input buffer 31.

Here, the operation of the delay adjustment circuit 34 is described.

FIG. 13 is a circuit diagram showing an example of the delay adjustmentcircuit 34.

Here, a case where the phases of differential input waveforms in thesignals IN and INB input to the delay adjustment circuit 34 are shiftedfrom each other, e.g. a case where the waveform of the signal INB enterslate as compared with the signal IN, is described.

The inverters 35-40 each have a configuration, in which a P-channel MOStransistor and an N-channel MOS transistor are coupled in series, asshown in FIG. 13.

First, when the signals IN and INB as shown in the view are input to thedelay adjustment circuit 34, the delay T3 that is a delay between thefalling of the signal IN and the rising of the signal INB will transmitto an input section (node 1 of FIG. 12) of the inverter 36 and an inputsection (node 2 of FIG. 12) of the inverter 39.

During the delay T3, the signal INB is ‘Low’ (the signal IN is also‘Low’), and the node 1 is ‘High’ (the node 2 is also ‘High’). Therefore,during the period of the delay T3, both the P-channel MOS transistor ofthe inverter 38 and the N-channel MOS transistor of the inverter 36 comeinto an ON state, and a shoot-through current (a dotted line of FIG. 12indicates the path of the shoot-through current) flows from the node 2to the node 3 (the input section of the inverter 37).

Then, when the waveform of the delayed signal INB arrives (the waveformrises), the P-channel MOS transistor of the inverter 38 is turned offand the shoot-through current stops. Because this shoot-through currentacts so as to prevent the waveform, which arrived early, at the node 3from falling, the shoot-through current is adjusted so that the fallingof the waveform at the node 3 is delayed and so that the delay isreduced.

Moreover, the delay T4 between the rising of the waveform of the signalIN and the falling of the waveform of the signal INB is also adjustedwith the same mechanism. (During the delay T4, both the N-channel MOStransistor of the inverter 38 and the P-channel MOS transistor of theinverter 36 come into an ON state, and a shoot-through current flowsfrom the node 3 to the node 2).

Also when the phase of the signal IN is delayed, as with the describedabove, a shoot-through current flows between the node 1 and the node 4(the input section of the inverter 40), and the early arriving signal isprevented from rising/falling and thus the delay is adjusted.

Note that, as shown in FIG. 12, when the delay adjustment circuit 34 isprovided in the I/O cell 89, to which the clock signals DQS and DQSB areinput, for the purpose of reducing the skew, the delay adjustmentcircuit is preferably provided also in the I/O cells 81-88 to which aninput data signal that is not the differential signals is input.

In this case, the connection is made so that a signal output from theoutput section of the I/O cell 81(-88) is input to one input section ofthe delay adjustment circuit 34 and so that the determination signal ofa signal output from the output section of the I/O cell 81(-88) is inputto the other input section of the delay adjustment circuit 34.

Thus, according to the Third Embodiment, a higher effect of reducing theskew can be obtained by providing the delay adjustment circuit 34 in theI/O cell 89 of the Second Embodiment described above (FIG. 11).

The present invention of the present inventor has been describedspecifically based on the embodiments, but it is obvious that thepresent invention is not limited to the embodiments and variousmodifications are possible without departing from the scope of theinvention.

1-16. (canceled)
 17. A memory device, comprising: a plurality ofexternal terminals; and a plurality of differential amplifier circuits,each being provided for a corresponding one of the external terminals,wherein each of the differential amplifier circuits comprises: a firstdifferential input section receiving a input signal from thecorresponding one of the external terminals; a second differential inputsection receiving a reference voltage; and a tail current sourceconnected commonly to the first differential input section and thesecond differential section and receiving a current of the firstdifferential input section and a current of the second differentialinput section, and wherein a current on the first differential inputsection side is detected and fed back to the tail current source so asto control a tail current flowing through the tail current source. 18.The memory device according to claim 17, wherein the current on thefirst differential input section side is converted to a voltage by meansof a resistor and the voltage, to which the resistor has converted, isfed back to the tail current source.
 19. The memory device according toclaim 17, further comprising: a first and a second transistorconstituting the first differential input section and the seconddifferential input section, respectively; a third transistor used as thetail current source of the first and the second transistor; and acurrent detection section detecting a current flowing through the firsttransistor, wherein the third transistor controls a current amount ofthe tail current in the tail current source based on a current which thecurrent detection section detects.
 20. The memory device according toclaim 19, wherein the current detection section includes a resistor forconverting the current flowing through the first transistor to avoltage, and wherein the third transistor has a gate to which thevoltage is supplied.
 21. A memory device comprising: a plurality ofexternal terminals each receiving data signal as data; and a pluralityof differential amplifier circuits, each being provided for acorresponding one of the external terminals, wherein each of thedifferential amplifier circuits comprises: a first differential inputsection including a first transistor coupled to a first node, the firsttransistor having a gate connected to the corresponding one of theexternal terminals; a second differential input section including asecond transistor coupled between a first power supply voltage line andthe first node, the second transistor having a gate to which a referencevoltage is applied; a tail current source including a third transistorcoupled between the first node and a second power supply line; and aresistor having a first and a second end, the first end coupled to thefirst power supply line and the second end coupled to the firsttransistor, wherein the third transistor has a gate coupled to thesecond end of the resistor.
 22. A memory device, comprising: a firstexternal terminal receiving a first signal of differential signal; asecond external terminal receiving a second signal that is an invertedsignal of the first signal of the differential signals; a firstdifferential amplifier circuit including a first differential inputsection receiving the first signal from the first external terminal anda second differential input section receiving a reference voltage, thefirst differential amplifier circuit carrying out a differentialamplification of the first signal and the reference voltage; and asecond differential amplifier circuit including a third differentialinput section receiving the second signal from the second externalterminal and a fourth differential input section receiving the referencevoltage, the second differential amplifier circuit carrying out adifferential amplification of the second signal and the referencevoltage, wherein the first differential amplifier circuit detects acurrent on the first differential input section side, and feeds thisback to a first tail current source of the first differential amplifiercircuit to control a tail current in the first tail current source, andwherein the second differential amplifier circuit detects a current onthe third differential input section side, and feeds this back to asecond tail current source of the second differential amplifier circuitto control a tail current in the second tail current source.
 23. Thememory device according to claim 22, further comprising a delay timeadjustment circuit, to which a first output signal output from the firstdifferential amplifier circuit and a second output signal from thesecond differential amplifier are input, and which adjusts so that adelay difference between the first output signal and the second outputsignal is substantially eliminated, and outputs the first output signaland the second output signal.
 24. The memory device according to claim22, wherein the first differential amplifier circuit includes a firstand a second transistor constituting the first differential inputsection and the second differential input section, respectively, a thirdtransistor coupled to the first and the second transistor to constitutethe first tail current source, and a first current detection sectiondetecting a current flowing through the first transistor, wherein thethird transistor controls a current amount of a tail current flowingthrough the third transistor based on the current which the firstcurrent detection section detects, wherein the second differentialamplifier circuit includes a fourth and a fifth transistor constitutingthe third differential input section and the fourth differential inputsection, respectively, a sixth transistor coupled to the fourth and thefifth transistor to constitute the second tail current source, and asecond current detection section detecting a current flowing through thefourth transistor, wherein the sixth transistor controls a currentamount of a tail current flowing through the sixth transistor based onthe current which the second current detection section detects.